How to reuse an instantiated module in verilog with updated inputs -

i have module :

module abc(   input  in1,   input  in2,   output in3 ); 

instantiating module in main module:

abc name_abc(in1, in2, out); 

now in1 changed based on other signal. understand, instantiation have created block of logic, want use block created different inputs or updated inputs. there way in verilog?

what want :

abc name_abc(in1_updated, in2, out); 

inputs continuous time signals. module instantiation not method call executing logic, therefore change in in1 value passed directly instance name_abc.

if mean use same module (hardware) being able switch between 2 data streams, imply mux in front of it.

wire   connect_to_abc_in; assign connect_to_abc_in = (select) ? in1 : in1_alternative ;