performancecounter - DTLB miss number counting discrepency -


i running linux on 32-nm intel westmere processor. have concern seemingly conflicting data on dtlb miss numbers performance counters. ran 2 experiments random memory access test program (single-threaded) follows:

experiment (1): counted dtlb misses using following performance counter

dtlb_misses.walk_completed ((event 49h, umask 02h)

experimt (2) counted dtlb misses summing following 2 counter value

mem_load_retired.dtlb_miss (event cbh, umask 80h)

and

mem_store_retired.dtlb_miss (event 0ch, umask 01h)

i expected output of these experiments similar. found numbers reported in experiment (1) twice of in experiment (2). @ loss why case.

can shed light on apparent discrepancy?

thanks

arka

that expected since first event counts number of misses tlb levels caused possible reasons (load, store, pre-fetch), including memory accesses performed speculatively, while other 2 events count retired (that is, non-speculative) load , store operations, , among them didn’t cause fault.

please refer chapter 19.6 of volume 3 of intel® 64 , ia-32 architectures software developer’s manual.

thanks,

stas


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