system verilog - Declaration of random packed associative array -
i wrote code initialize packed associative array in following fashion.
int msize = $urandom_range(20) ; bit [0:3] [0:msize] mem [int] ; but, showing error : "illegal operand constant expression"
alternative one.
the dimensions of packed portion of array must consistent, decided @ compile time. assignment of msize decided @ run time. make msize parameter assigned @ compile time.
alternatively, if want mem have random msize @ run time, mem should defined as:
bit [0:3] mem [int] []; before accessing element should put:
if(!mem.exists(lookup_id)) mem[int_key_address] = new[msize]; read arrays in systemverilog in § 7 of ieee std 1800-2012, free ieee website.
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